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cy62157esl mobl ? 8-mbit (512 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-43141 rev. *e revised june 4, 2013 8-mbit (512 k 16) static ram features very high speed: 45 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a ultra low active power ? typical active current: 1.8 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 44-pin thin small outline package (tsop) ii package functional description the cy62157esl is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications. the device also has an automatic power down feature that si gnificantly reduces power consumption when addresses are not toggling. plac e the device into standby mode when deselected (ce high or both bhe and ble are high). the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), both the byte high enable and the byte low enable are disabled (bhe , ble high), or during an active write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. the cy62157esl device is suitable for interfacing with processors that have ttl i/p levels. it is not suitable for processors that require cmos i/p levels. please see electrical characteristics on page 4 for more details and suggested alternatives. logic block diagram 512 k 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 10 a 18 ce power down circuit bhe ble ce
cy62157esl mobl ? document number: 001-43141 rev. *e page 2 of 17 contents pin configurations ........................................................... 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17
cy62157esl mobl ? document number: 001-43141 rev. *e page 3 of 17 pin configurations figure 1. 44-pin tsop ii pinout (top view) 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 3 a 2 a 1 a 0 a 17 a 4 a 9 a 10 a 11 a 12 a 15 a 16 oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss 10 a 18 a 14 a 8 a 13 product portfolio product range v cc range (v) [1] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1mhz f = f max typ [2] max typ [2] max typ [2] max cy62157esl industrial 2.2 v?3.6 v and 4.5 v?5.5 v 45 1.8 3 18 25 2 8 notes 1. datasheet specifications are not guaranteed for v cc in the range of 3.6 v to 4.5 v. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c.
cy62157esl mobl ? document number: 001-43141 rev. *e page 4 of 17 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage to ground potentia l ............. ..?0.5 v to 6.0 v dc voltage applied to outputs in high z state [3, 4] ........................................?0.5 v to 6.0 v dc input voltage [3, 4] ....................................?0.5 v to 6.0 v output current into outputs (low) ............................ 20 ma static discharge voltage (mil-std-883, method 3015) .................................. >2001 v latch up current ..................................................... >200 ma operating range device range ambient temperature v cc [5] cy62157esl industrial ?40 c to +85 c 2.2 v?3.6 v, and 4.5 v?5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [6] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?0.1 ma ? ? 3.4 [7] v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 4.5 < v cc < 5.5 ?0.5 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma, cmos levels ?1825ma f = 1 mhz ? 1.8 3 i sb1 [8] automatic ce power down current ? cmos inputs ce > v cc ?? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) ?28 ? a i sb2 [8] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?28 ? a notes 3. v il (min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 7. please note that the maximum v oh limit does not exceed minimum cmos v ih of 3.5 v. if you are interfacing this sram with 5 v legacy processors that require a minimum v ih of 3.5 v, please refer to application note an6081 for technical details and options you may consider. 8. chip enable (ce ) needs to be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating.
cy62157esl mobl ? document number: 001-43141 rev. *e page 5 of 17 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 ? c/w ? jc thermal resistance (junction to case) 13 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th parameters 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 ? r2 15385 1554 990 ? r th 8000 645 639 ? v th 1.20 1.75 1.77 v note 9. tested initially and after any design or proc ess changes that may affect these parameters .
cy62157esl mobl ? document number: 001-43141 rev. *e page 6 of 17 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v v cc = 1.5 v ? 2 5 ? a v cc = 2.0 v ? 2 8 t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce or bhe .ble [14] notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 11. chip enable (ce ) needs to be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating. 12. tested initially and after any design or process changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 14. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling chip enable signals or by disabling both bhe and ble .
cy62157esl mobl ? document number: 001-43141 rev. *e page 7 of 17 switching characteristics over the operating range parameter [15] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [16] 5 ? ns t hzoe oe high to high z [16, 17] ? 18 ns t lzce ce low to low z [16] 10 ? ns t hzce ce high to high z [16, 17] ? 18 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 45 ns t dbe ble /bhe low to data valid ? 45 ns t lzbe ble /bhe low to low z [16, 18] 5 ? ns t hzbe ble /bhe high to high z [16, 17] ? 18 ns write cycle [19] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [16, 17] ? 18 ns t lzwe we high to low z [16] 10 ? ns notes 15. test conditions for all parameters other than tri-state paramet ers assume signal transition time of 3 ns or less, timing ref erence levels of 1.5 v, input pulse levels of 0 to 3 v, and output loading of the specified iol/ioh as shown in the figure 2 on page 5 . 16. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 18. if both byte enables are toggled together, this value is 10 ns. 19. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write.
cy62157esl mobl ? document number: 001-43141 rev. *e page 8 of 17 switching waveforms figure 4. read cycle no.1: address transition controlled . [20, 21] figure 5. read cycle no. 2: oe controlled [21, 22] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 20. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 21. we is high for read cycle. 22. address valid before or similar to ce , bhe , ble transition low.
cy62157esl mobl ? document number: 001-43141 rev. *e page 9 of 17 figure 6. write cycle no 1: we controlled [23, 24] figure 7. write cycle 2: ce controlled [23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data in note 25 t bw t sce data i/o address ce we bhe /ble t hd t sd t pwe t ha t aw t sce t wc data in t bw t sa ce address we data i/o bhe /ble note 25 notes 23. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. 24. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period, the i/os are in output state. do not apply input signals.
cy62157esl mobl ? document number: 001-43141 rev. *e page 10 of 17 figure 8. write cycle 3: bhe /ble controlled [26, 27] switching waveforms (continued) t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 28 data i/o address ce we bhe /ble notes 26. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inac tive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. 27. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period, the i/os are in output state. do not apply input signals.
cy62157esl mobl ? document number: 001-43141 rev. *e page 11 of 17 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power down standby (i sb ) x [29] x x h h high z deselect/power down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 29. the ?x? (don?t care) state for the chip enable in the truth table refers to the logic state (either high or low). intermedia te voltage levels on this pin is not permitted.
cy62157esl mobl ? document number: 001-43141 rev. *e page 12 of 17 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 CY62157ESL-45ZSXI 51-85087 44-pin tsop type ii (pb-free) industrial temperature range: i = industrial pb-free package type: zs = 44-pin tsop ii speed grade: 45 ns voltage range: sl = 3 v typical; 5 v typical process technology: e = 90 nm buswidth: 7 = 16 density: 5 = 8-mbit family code: mobl sram family company id: cy = cypress cy x 45 zs 621 5 7 e sl - i
cy62157esl mobl ? document number: 001-43141 rev. *e page 13 of 17 package diagram figure 9. 44-pin tsop z44-ii package outline, 51-85087 51-85087 *e
cy62157esl mobl ? document number: 001-43141 rev. *e page 14 of 17 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degrees celsius mhz megahertz ? a microampere ma milliampere ns nanosecond ? ohm pf picofarad v volt w watt
cy62157esl mobl ? document number: 001-43141 rev. *e page 15 of 17 document history page document title: cy62157esl mobl ? , 8-mbit (512 k 16) static ram document number: 001-43141 rev. ecn no. issue date orig. of change description of change ** 1875228 see ecn vkn / aesa new data sheet. *a 2943752 06/03/2010 vkn added contents . updated electrical characteristics : added note 8 and referred the same note in i sb2 parameter. updated truth table : added note 29 and referred the same note in ce column. updated package diagram . added sales, solutions, and legal information . *b 3109266 12/13/2010 pras changed ta ble footnotes to footnotes. added ordering code definitions . *c 3295175 06/29/2011 rame updated functional description : remove reference to an10 64 sram system guidelines. updated electrical characteristics : updated note 8 (added i sb1 ) and referred the same note in i sb1 parameter. updated capacitance : added note 9 and referred the same note in parameter column. updated thermal resistance : added note 9 and referred the same note in parameter column. updated data retention characteristics : added note 11 and referred the same note in i ccdr parameter. updated ordering code definitions . added units of measure . *d 3904207 02/14/2013 memj updated switching waveforms : updated figure 6 (removed oe signal). updated figure 7 (removed oe signal). removed the note ?data i/o is high impedance if oe = v ih .? and its reference in figure 6 , figure 7 . removed the figure ?write cycle 3: we controlled, oe low?. updated figure 8 (removed ?oe low? in caption only). removed the note ?data i/o is high impedance if oe = v ih .? and its reference in figure 8 . updated package diagram : spec 51-85087 ? changed revision from *c to *e.
cy62157esl mobl ? document number: 001-43141 rev. *e page 16 of 17 *e 4019657 06/04/2013 memj updated functional description . updated electrical characteristics : added one more test condition ?4.5 < v cc < 5.5, i oh = ?0.1 ma? for v oh parameter and added maximum value corresponding to that test condition. added note 7 and referred the same note in maximum value for v oh parameter corresponding to test condition ?4.5 < v cc < 5.5, i oh = ?0.1 ma?. document history page (continued) document title: cy62157esl mobl ? , 8-mbit (512 k 16) static ram document number: 001-43141 rev. ecn no. issue date orig. of change description of change
document number: 001-43141 rev. *e revised june 4, 2013 page 17 of 17 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. cy62157esl mobl ? ? cypress semiconductor corporation, 2008?2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assume s no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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